XD2000F™ Development SystemXtremeData's XD2000F™ development system is a complete platform on which to explore the benefits of FPGA coprocessing within an x86 COTS computing environment. The development system ships with a full complement of hardware, software, and FPGA IP so users can immediately begin developing their FPGA-accelerated applications. The hardware includes a Linux®-based PC tower and monitor. Inside the tower is a dual Opteron™ motherboard populated with one AMD® Opteron™ processor and one XD2000F FPGA Coprocessor Module. The XD2000F™, installed in the second Opteron™ (1207) processor socket, uses the motherboard's existing CPU infrastructure to create a full-featured environment for FPGA coprocessor functions. The high-bandwidth, low-latency HyperTransport™ link between the XD2000F™ and the Opteron™ enables tightly-coupled FPGA acceleration of x86 applications previously impossible with legacy PCI-bus based solutions. The XD2000F's JTAG interface is cabled to a back panel connector for easy access, and allows Altera’s SignalTap® software to provide waveform viewing of signals in the FPGA fabric . The development system supports a number of FPGA configuration options. The Application FPGA can be configured directly via JTAG using the supplied USB Blaster cable or download from hard disk over the HT links. After system power-up, the Bridge FPGA is automatically loaded with the configuration file resident in the default FLASH location. Application software running on the Opteron™ can store and load FPGA configuration images that are located on the hard disk. The development system ships with a full suite of Altera's industry leading FPGA development tools, including 1- year licenses for Quartus® II, SOPC Builder, the Nios® II Embedded Design Suite, and even the C-to-Hardware Acceleration Compiler called C2H. XtremeData provides an open source Linux device driver which allows user space applications to directly access memory mapped FPGA resources, service FPGA interrupt requests, lock physical memory, and perform FPGA controlled DMAs.
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