Tightly Coupling FPGAs and GPPs

This article highlights the benefits of Acceleration Abstraction Layers and discusses how military systems designers can now leverage a new class of COTS board and accelerator modules to solve some of their most demanding tasks.

Radar, cryptography, and Software Defined Radio (SDR) applications can often benefit from being run on FPGAs tightly coupled with multi-core, general-purpose processors. But until now, makers of FPGA devices have had to develop proprietary accelerator middleware so that platform-level services would be accessible from their products. This adds cost to In-Socket accelerator products and may lock application software into specific accelerators, or even specific accelerator generations. Intel QuickAssist Technology includes both third-party In-Socket Accelerator (ISA) FPGA modules and an Acceleration Abstraction Layer (AAL) developed by Intel. AAL provides a consistent interface for application software so that underlying accelerator and general-purpose processor hardware can evolve independently and application software can more easily scale.

Uncovering the Issues of both GPP and FPGA

Radar, cryptography, SDR, and real-time surveillance video processing are examples of military applications whose workloads are highly parallel. Over the years many solutions have been deployed that run on COTS general-purpose processor (GPP) blades. Using general-purpose processors rather than specialized hardware accelerators are cost-effective since software is typically easier to develop, can scale from small to large systems, and can be easily ported to new processor generations. Using GPPs to do all the processing may not be the most effective approach, especially when a platform's Size, Weight, and Power (SWaP) are constrained, or when extremely high-performance at high-efficiency are required.

FPGAs and GPPs: a good couple?

FPGAs require less power than GPPs of similar signal processing performance. Power savings is obviously important for UAVs, for example, where lightweight power and cooling systems can translate directly into larger fuel tanks that enable the craft to fly further and faster. Real-time performance is another key parameter, as when a system is trying to track a moving target. FPGA accelerators can process some classes of signal and image processing algorithms faster than GPPs, which decreases the time to compute and can help save lives.

FPGAs, however, don't excel at every type of processing that modern integrated systems must handle. Many military applications have been designed to run on hybrid systems with tightly coupled GPPs and FPGAs.

But developing such customized GPP plus FPGA boards is time-consuming and expensive. It can take six months or longer to design and build a complex custom PCB containing processor(s), FPGA(s), memory, interfaces, and other components. Issues uncovered during hardware validation may require "blue wires". So boards may need to be re-spun, which adds cost and delay. Even after a new board boots correctly, application code developers must wait until communication mechanisms are designed, built, and debugged so that their application software will interface to the board hardware. This communication layer adds to the cost of developing new accelerator technology. It also locks in application software to the specific communication mechanism used on a specific board design. Software may need to be substantially changed when board design changes or even when new versions of accelerators are released.

This leaves such non-COTS-based solutions in a vulnerable state. EOL issues can happen at any time, even with major components, as the recent, unexpected removal of PA Semi and their future products demonstrates. Just as bad is that processor and FPGA technology is evolving so quickly that a custom PCB can be obsolete the day it is released to production.

Lastly, feature creep can get in the way as new requirements emerge from the battlefield that require larger amounts of processing, less power, or even different mechanicals. If more sockets, more cores, or a higher mix of FPGA to CPU are now required, the designer is forced into a new spin of the board to meet new requirements. These new challenges equal higher cost, longer project delays, and increased room for competition to get to the market first.

Until recently the lack of flexible, COTS-based solutions that tightly couple FPGAs to CPUs have pretty much dictated a custom design route. But ultimately, custom designs can be the reason your project misses requirements, budgets, or future product life targets.

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